1. Field of the Invention
The present invention relates to a dummy pattern placement apparatus, method and program, and a semiconductor device. In particular, the present invention relates to a dummy pattern placement apparatus, method and program capable of simplifying OPC (Optical Proximity Correction) processing, and a semiconductor device.
2. Description of the Related Art
In recent years, in semiconductor devices, multi-layering of a wiring layer has been making progress. If a plurality of wiring layers are deposited one after another, the upper wiring layer is affected more by the unevenness in the surfaces of lower wiring layers. If this effect is large, even disconnection may occur in the wiring of a wiring layer formed in the upper layer. Moreover, a disconnection of wiring may occur due to the local unevenness even in the same wiring layer. In order to solve this problem, there is known a technique in which a dummy pattern is placed so as not to overlap with a wiring pattern. Note that the dummy pattern is placed also in order to make uniform the layer thickness of the wiring layer and prevent a variation in the wiring resistance other than in order to prevent the disconnection of the wiring. Although the dummy pattern may be set to have a power supply potential, it is typically set to be floating (a state where the dummy pattern is connected nowhere).
Moreover, the reduction of the distance between wirings has also been making progress. Then, in order to address a problem that the accuracy of pattern shape cannot be secured due to the effect of interference of light incident through a photomask, the OPC processing (optical proximity correction processing) is carried out on layout data after pattern placement. In the OPC processing, a hammerhead pattern is placed in an end part of a pattern, or the width of a pattern is thickened or thinned. Hereinafter, the process of thickening or thinning the width of a pattern is called bias processing.
Japanese Patent Application Publications Nos. 2001-230250 and 2004-354605 describe the placement of a dummy pattern. Japanese Patent Application Publication No. 2001-230250 discloses a technique, in which a dummy pattern is placed near both sides of pattern end parts in order to prevent occurrence of a variation in line end parts during etching. Japanese Patent Application Publication No. 2004-354605 discloses a technique, in which a dummy pattern is placed around a wiring pattern to add a hammerhead pattern according to a certain rule. In addition, Japanese Patent Application Publication No. 2001-100390 discloses a technique related to the pattern correction of an exposure mask.
As described above, a dummy pattern needs to be placed in order to secure the reliability of a semiconductor device. In this case, the OPC processing needs to be carried out on the wiring pattern in consideration of the placed dummy pattern, however, depending on the form of placement of the dummy pattern, especially the work load of the bias processing increases significantly or the time required for the bias processing is prolonged.
For example, in the case where fine dummy patterns are irregularly placed beside a long wiring pattern, the distances between the dummy patterns and the wiring pattern are relatively irregular, and thus the data amount of a table that stores the correction values of the bias processing increases.
Thus, the load of the OPC processing (especially, the load of the bias processing) has been increasing due to the optical effects involved in the placement of the dummy pattern.